ATNEL tech-forum 2018-08-09T10:36:26+01:00 https://forum.atnel.pl/feed.php?f=8&t=21103&mode 2018-08-09T10:36:26+01:00 2018-08-09T10:36:26+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210581#p210581 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> Statystyki: Napisane przez micky — 9 sie 2018, o 10:36

]]> 2018-08-08T06:25:49+01:00 2018-08-08T06:25:49+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210556#p210556 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> micky napisał(a):

Odpal Mirkowy i2c scanner. Bo adres wypluty z Arduinowego scannera trza pomnożyć przez 2 tak jak kolega wcześniej pisał. Może masz złe kontakty, że kapryśnie działa?


Niestety programy Mirka, o ile bardzo przydatne dlamnie bezużyteczne ponieważ nigdzie nie mam Windowsa ;)

Nie mniej dzięki za podpowiedzi, będę analizował dalej bo dzisiaj kolega w pracy podrzuci mi analizator stanów logicznych.

Statystyki: Napisane przez GoRo3 — 8 sie 2018, o 06:25

]]> 2018-08-08T05:20:11+01:00 2018-08-08T05:20:11+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210554#p210554 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> Statystyki: Napisane przez micky — 8 sie 2018, o 05:20

]]> 2018-08-07T22:20:30+01:00 2018-08-07T22:20:30+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210545#p210545 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]>
Mam rezystory 4,7K pod Vcc podpięte. A0,A1,A2 pod GND. Skaner pluje adresem 0x38, więc taki testowałem, jak i również całą iterację po puli adresów.

Chociaż teraz mam dziwną rzeczy. NIby coś się ruszyło na adresie 0x70, jednak dioda kontrolna ciągle mi zgłasza błąd nr 0x05 czyli według biblioteki:
[syntax=c]USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data[/syntax]

Oraz jest dosyć kapryśny, nie działa za każdym razem ale ruszyło.... Wiecie co to może być?

Statystyki: Napisane przez GoRo3 — 7 sie 2018, o 22:20

]]> 2018-08-07T20:42:02+01:00 2018-08-07T20:42:02+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210540#p210540 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> krish napisał(a):

Oczywiście najlepiej przeskanować sobie wszystkie adresy i2c.

Dokładnie ;) albo zajrzeć do noty PDF swojej wersji scalaka gdzie jest podany adres

Statystyki: Napisane przez mirekk36 — 7 sie 2018, o 20:42

]]> 2018-08-07T21:09:45+01:00 2018-08-07T20:38:14+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210539#p210539 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> Oczywiście najlepiej przeskanować sobie wszystkie adresy i2c.

Statystyki: Napisane przez krish — 7 sie 2018, o 20:38

]]> 2018-08-07T20:15:21+01:00 2018-08-07T20:15:21+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210538#p210538 <![CDATA[Re: USI AVR + PCF8574AP - problem z komunikacją]]> Myślę, że jak zwykle w takich wypadkach masz coś źle z adresem na szynie I2C.
Napisz jak masz podłączone piny A0,A1,A2 bo od tego zależy adres układu - to po pierwsze
Arduino korzysta z adresowania 7bit, biblioteki dla AVR-a przeważnie z adresu 8bit gdzie ostatni bit jest "0" lub "1" w zależności czy czytasz układ czy do niego zapisujesz.
Oczywiście linie I2C masz sprzętowo podciągnięte rezystorami do Vcc?

Statystyki: Napisane przez mczarny — 7 sie 2018, o 20:15

]]> 2018-08-07T19:27:47+01:00 2018-08-07T19:27:47+01:00 https://forum.atnel.pl/viewtopic.php?t=21103&p=210536#p210536 <![CDATA[USI AVR + PCF8574AP - problem z komunikacją]]>
Niestety muszę przyznać, że poległem w kwesti ustawienia USI na AtTinny 85 aby móc komunikować się po i2c z urządzeniem PCF8574AP. :oops:

Proszę szanowne grono o pomoc w mojej kwestii bo już nie wiem co jest nie tak a siedzę nad tym od 4 dni (cały weekend zmarnowany:( ).

Chciałem napisać własny sterownik do rejestru przesównego pod i2c + LCD. Niestety po podłączeniu wszystkiego oraz skonfigurowaniu biblioteki z noty AVR (AVR310 - USI Master), rejestr nawet nie drgnie. Tzn diody jakie podpiołem nie chcą się świecić. Diody do PCF'a są podpięte anodą do + przez rezystor do nóżki scalaka. Dodam, że jak podłączam pod arduino i puszczam prosty program do sterowania i2c to wszystko działa, tylko na moim AVR nie chcę.

Próbowałem już wszystkiego co znalazłem na sieci żadne rozwiązanie niestety nie działa a mnie dodatkowo irytuje to, że na forach angielskich nikt nie ma z tą biblioteką problemów.

Poniżej przesyłam kod, w którym próbuje wysłać sygnał na każdy adres po kolei. Niestety i to nie działa. Macie może jakąś podpowiedź do tego?

dodatkowo, adres w deklaracji define to adres jaki mi wypluł i2c scanner na arduino. Próbowałem się z nim komunikować ale bez rezultatu.

[syntax=c]#include <avr/io.h>
#include <inttypes.h>
#include <util/delay.h>
#include <avr/interrupt.h>

#include "USI_TWI_MASTER.h"

#define ADDR 0x38

void prtnt_state(uint8_t state) {
for (int i = 0; i <= state; i++) {

PORTB |= (1 << PB4);
_delay_ms(225);
PORTB &= ~(1 << PB4);
_delay_ms(225);
}
}

int main(void) {

uint8_t buffer[2];
uint8_t TWI_targetSlaveAddress;
static unsigned char state;
uint8_t i = 0;

PORTB |= (1 << PB4);
DDRB |= (1 << PB4);
PORTB &= ~(1 << PB4);

TWI_targetSlaveAddress = ADDR;

buffer[0] = (TWI_targetSlaveAddress << TWI_ADR_BITS) | 0;
buffer[1] = 0x00;

USI_TWI_Master_Initialise();

while (1) {

_delay_ms(2500);

while (i < 0xff) {

buffer[0] = (i << TWI_ADR_BITS) | 0;
state = USI_TWI_Start_Transceiver_With_Data(buffer, 2);

i++;
}

if (!state) {
prtnt_state(USI_TWI_Get_State_Info());
}
}
return 0;

}[/syntax]

bibioteka USI_MASTER.h:
[syntax=c]/*****************************************************************************
*
* Atmel Corporation
*
* File : USI_TWI_Master.h
* Compiler : AVRGCC Toolchain version 3.4.2
* Revision : $Revision: 992 $
* Date : $Date: 2013-11-07 $
* Updated by : $Author: Atmel $
*
* Support mail : avr@atmel.com
*
* Supported devices : All device with USI module can be used.
* The example is written for the ATmega169, ATtiny26 and ATtiny2313
*
* AppNote : AVR310 - Using the USI module as a TWI Master
*
* Description : This is an implementation of an TWI master using
* the USI module as basis. The implementation assumes the AVR to
* be the only TWI master in the system and can therefore not be
* used in a multi-master system.
* Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise()
* function. Hence messages/data are transceived on the bus using
* the USI_TWI_Start_Transceiver_With_Data() function. If the transceiver
* returns with a fail, then use USI_TWI_Get_Status_Info to evaluate the
* couse of the failure.
*
****************************************************************************/
#include<avr/io.h>
//********** Defines **********//

// Defines controlling timing limits
//#define TWI_FAST_MODE

#define SYS_CLK 4000.0 // [kHz]

#ifdef TWI_FAST_MODE // TWI FAST mode timing limits. SCL = 100-400kHz
#define T2_TWI ((SYS_CLK *1300) /1000000) +1 // >1,3us
#define T4_TWI ((SYS_CLK * 600) /1000000) +1 // >0,6us

#else // TWI STANDARD mode timing limits. SCL <= 100kHz
#define T2_TWI ((SYS_CLK *4700) /1000000) +1 // >4,7us
#define T4_TWI ((SYS_CLK *4000) /1000000) +1 // >4,0us
#endif

// Defines controling code generating
//#define PARAM_VERIFICATION
//#define NOISE_TESTING
//#define SIGNAL_VERIFY

//USI_TWI messages and flags and bit masks
//#define SUCCESS 7
//#define MSG 0
/****************************************************************************
Bit and byte definitions
****************************************************************************/
#define TWI_READ_BIT 0 // Bit position for R/W bit in "address byte".
#define TWI_ADR_BITS 1 // Bit position for LSB of the slave address bits in the init byte.
#define TWI_NACK_BIT 0 // Bit position for (N)ACK bit.

#define USI_TWI_NO_DATA 0x00 // Transmission buffer is empty
#define USI_TWI_DATA_OUT_OF_BOUND 0x01 // Transmission buffer is outside SRAM space
#define USI_TWI_UE_START_CON 0x02 // Unexpected Start Condition
#define USI_TWI_UE_STOP_CON 0x03 // Unexpected Stop Condition
#define USI_TWI_UE_DATA_COL 0x04 // Unexpected Data Collision (arbitration)
#define USI_TWI_NO_ACK_ON_DATA 0x05 // The slave did not acknowledge all data
#define USI_TWI_NO_ACK_ON_ADDRESS 0x06 // The slave did not acknowledge the address
#define USI_TWI_MISSING_START_CON 0x07 // Generated Start Condition not detected on bus
#define USI_TWI_MISSING_STOP_CON 0x08 // Generated Stop Condition not detected on bus

// Device dependant defines

#if defined(__AVR_AT90Mega169__) | defined(__AVR_ATmega169PA__) | \
defined(__AVR_AT90Mega165__) | defined(__AVR_ATmega165__) | \
defined(__AVR_ATmega325__) | defined(__AVR_ATmega3250__) | \
defined(__AVR_ATmega645__) | defined(__AVR_ATmega6450__) | \
defined(__AVR_ATmega329__) | defined(__AVR_ATmega3290__) | \
defined(__AVR_ATmega649__) | defined(__AVR_ATmega6490__)
#define DDR_USI DDRE
#define PORT_USI PORTE
#define PIN_USI PINE
#define PORT_USI_SDA PORTE5
#define PORT_USI_SCL PORTE4
#define PIN_USI_SDA PINE5
#define PIN_USI_SCL PINE4
#endif

#if defined(__AVR_ATtiny25__) | defined(__AVR_ATtiny45__) | defined(__AVR_ATtiny85__) | \
defined(__AVR_AT90Tiny26__) | defined(__AVR_ATtiny26__)
#define DDR_USI DDRB
#define PORT_USI PORTB
#define PIN_USI PINB
#define PORT_USI_SDA PORTB0
#define PORT_USI_SCL PORTB2
#define PIN_USI_SDA PINB0
#define PIN_USI_SCL PINB2
#endif

#if defined(__AVR_AT90Tiny2313__) | defined(__AVR_ATtiny2313__)
#define DDR_USI DDRB
#define PORT_USI PORTB
#define PIN_USI PINB
#define PORT_USI_SDA PORTB5
#define PORT_USI_SCL PORTB7
#define PIN_USI_SDA PINB5
#define PIN_USI_SCL PINB7
#endif

// General defines
#define TRUE 1
#define FALSE 0

//********** Prototypes **********//

void USI_TWI_Master_Initialise( void );
unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char * , unsigned char );
unsigned char USI_TWI_Get_State_Info( void );[/syntax]

USI_Master.c:
[syntax=c]/*****************************************************************************
*
* Atmel Corporation
*
* File : USI_TWI_Master.c
* Compiler : AVRGCC Toolchain version 3.4.2
* Revision : $Revision: 992 $
* Date : $Date: 2013-11-07 $
* Updated by : $Author: Atmel $
*
* Support mail : avr@atmel.com
*
* Supported devices : All device with USI module can be used.
* The example is written for the ATmega169, ATtiny26 and ATtiny2313
*
* AppNote : AVR310 - Using the USI module as a TWI Master
*
* Description : This is an implementation of an TWI master using
* the USI module as basis. The implementation assumes the AVR to
* be the only TWI master in the system and can therefore not be
* used in a multi-master system.
* Usage : Initialize the USI module by calling the USI_TWI_Master_Initialise()
* function. Hence messages/data are transceived on the bus using
* the USI_TWI_Transceive() function. The transceive function
* returns a status byte, which can be used to evaluate the
* success of the transmission.
*
****************************************************************************/
#include <avr/io.h>
#include "USI_TWI_Master.h"
#include <util/delay.h>

unsigned char USI_TWI_Master_Transfer( unsigned char );
unsigned char USI_TWI_Master_Stop( void );

union USI_TWI_state
{
unsigned char errorState; // Can reuse the TWI_state for error states due to that it will not be need if there exists an error.
struct
{
unsigned char addressMode : 1;
unsigned char masterWriteDataMode : 1;
unsigned char unused : 6;
};
} USI_TWI_state;

/*---------------------------------------------------------------
USI TWI single master initialization function
---------------------------------------------------------------*/
void USI_TWI_Master_Initialise( void )
{
PORT_USI |= (1<<PIN_USI_SDA); // Enable pullup on SDA, to set high as released state.
PORT_USI |= (1<<PIN_USI_SCL); // Enable pullup on SCL, to set high as released state.

DDR_USI |= (1<<PIN_USI_SCL); // Enable SCL as output.
DDR_USI |= (1<<PIN_USI_SDA); // Enable SDA as output.

USIDR = 0xFF; // Preload dataregister with "released level" data.
USICR = (0<<USISIE)|(0<<USIOIE)| // Disable Interrupts.
(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode.
(1<<USICS1)|(0<<USICS0)|(1<<USICLK)| // Software stobe as counter clock source
(0<<USITC);
USISR = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Clear flags,
(0x0<<USICNT0); // and reset counter.
}

/*---------------------------------------------------------------
Use this function to get hold of the error message from the last transmission
---------------------------------------------------------------*/
unsigned char USI_TWI_Get_State_Info( void )
{
return ( USI_TWI_state.errorState ); // Return error state.
}

/*---------------------------------------------------------------
USI Transmit and receive function. LSB of first byte in data
indicates if a read or write cycles is performed. If set a read
operation is performed.

Function generates (Repeated) Start Condition, sends address and
R/W, Reads/Writes Data, and verifies/sends ACK.

Success or error code is returned. Error codes are defined in
USI_TWI_Master.h
---------------------------------------------------------------*/
unsigned char USI_TWI_Start_Transceiver_With_Data( unsigned char *msg, unsigned char msgSize)
{
unsigned char tempUSISR_8bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0x0<<USICNT0); // set USI to shift 8 bits i.e. count 16 clock edges.
unsigned char tempUSISR_1bit = (1<<USISIF)|(1<<USIOIF)|(1<<USIPF)|(1<<USIDC)| // Prepare register value to: Clear flags, and
(0xE<<USICNT0); // set USI to shift 1 bit i.e. count 2 clock edges.

USI_TWI_state.errorState = 0;
USI_TWI_state.addressMode = TRUE;

#ifdef PARAM_VERIFICATION
if(msg > (unsigned char*)RAMEND) // Test if address is outside SRAM space
{
USI_TWI_state.errorState = USI_TWI_DATA_OUT_OF_BOUND;
return (FALSE);
}
if(msgSize <= 1) // Test if the transmission buffer is empty
{
USI_TWI_state.errorState = USI_TWI_NO_DATA;
return (FALSE);
}
#endif

#ifdef NOISE_TESTING // Test if any unexpected conditions have arrived prior to this execution.
if( USISR & (1<<USISIF) )
{
USI_TWI_state.errorState = USI_TWI_UE_START_CON;
return (FALSE);
}
if( USISR & (1<<USIPF) )
{
USI_TWI_state.errorState = USI_TWI_UE_STOP_CON;
return (FALSE);
}
if( USISR & (1<<USIDC) )
{
USI_TWI_state.errorState = USI_TWI_UE_DATA_COL;
return (FALSE);
}
#endif

if ( !(*msg & (1<<TWI_READ_BIT)) ) // The LSB in the address byte determines if is a masterRead or masterWrite operation.
{
USI_TWI_state.masterWriteDataMode = TRUE;
}

/* Release SCL to ensure that (repeated) Start can be performed */
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Verify that SCL becomes high.
#ifdef TWI_FAST_MODE
_delay_us( T4_TWI/4 ); // Delay for T4TWI if TWI_FAST_MODE
#else
_delay_us( T2_TWI/4 ); // Delay for T2TWI if TWI_STANDARD_MODE
#endif

/* Generate Start Condition */
PORT_USI &= ~(1<<PIN_USI_SDA); // Force SDA LOW.
_delay_us( T4_TWI/4 );
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.

#ifdef SIGNAL_VERIFY
if( !(USISR & (1<<USISIF)) )
{
USI_TWI_state.errorState = USI_TWI_MISSING_START_CON;
return (FALSE);
}
#endif

/*Write address and Read/Write data */
do
{
/* If masterWrite cycle (or inital address tranmission)*/
if (USI_TWI_state.addressMode || USI_TWI_state.masterWriteDataMode)
{
/* Write a byte */
PORT_USI &= ~(1<<PIN_USI_SCL); // Pull SCL LOW.
USIDR = *(msg++); // Setup data.
USI_TWI_Master_Transfer( tempUSISR_8bit ); // Send 8 bits on bus.

/* Clock and verify (N)ACK from slave */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
if( USI_TWI_Master_Transfer( tempUSISR_1bit ) & (1<<TWI_NACK_BIT) )
{
if ( USI_TWI_state.addressMode )
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_ADDRESS;
else
USI_TWI_state.errorState = USI_TWI_NO_ACK_ON_DATA;
return (FALSE);
}
USI_TWI_state.addressMode = FALSE; // Only perform address transmission once.
}
/* Else masterRead cycle*/
else
{
/* Read a data byte */
DDR_USI &= ~(1<<PIN_USI_SDA); // Enable SDA as input.
*(msg++) = USI_TWI_Master_Transfer( tempUSISR_8bit );

/* Prepare to generate ACK (or NACK in case of End Of Transmission) */
if( msgSize == 1) // If transmission of last byte was performed.
{
USIDR = 0xFF; // Load NACK to confirm End Of Transmission.
}
else
{
USIDR = 0x00; // Load ACK. Set data register bit 7 (output for SDA) low.
}
USI_TWI_Master_Transfer( tempUSISR_1bit ); // Generate ACK/NACK.
}
}while( --msgSize) ; // Until all data sent/received.

USI_TWI_Master_Stop(); // Send a STOP condition on the TWI bus.

/* Transmission successfully completed*/
return (TRUE);
}

/*---------------------------------------------------------------
Core function for shifting data in and out from the USI.
Data to be sent has to be placed into the USIDR prior to calling
this function. Data read, will be return'ed from the function.
---------------------------------------------------------------*/
unsigned char USI_TWI_Master_Transfer( unsigned char temp )
{
USISR = temp; // Set USISR according to temp.
// Prepare clocking.
temp = (0<<USISIE)|(0<<USIOIE)| // Interrupts disabled
(1<<USIWM1)|(0<<USIWM0)| // Set USI in Two-wire mode.
(1<<USICS1)|(0<<USICS0)|(1<<USICLK)| // Software clock strobe as source.
(1<<USITC); // Toggle Clock Port.
do
{
_delay_us( T2_TWI/4 );
USICR = temp; // Generate positve SCL edge.
while( !(PIN_USI & (1<<PIN_USI_SCL)) );// Wait for SCL to go high.
_delay_us( T4_TWI/4 );
USICR = temp; // Generate negative SCL edge.
}while( !(USISR & (1<<USIOIF)) ); // Check for transfer complete.

_delay_us( T2_TWI/4 );
temp = USIDR; // Read out data.
USIDR = 0xFF; // Release SDA.
DDR_USI |= (1<<PIN_USI_SDA); // Enable SDA as output.

return temp; // Return the data from the USIDR
}

/*---------------------------------------------------------------
Function for generating a TWI Stop Condition. Used to release
the TWI bus.
---------------------------------------------------------------*/
unsigned char USI_TWI_Master_Stop( void )
{
PORT_USI &= ~(1<<PIN_USI_SDA); // Pull SDA low.
PORT_USI |= (1<<PIN_USI_SCL); // Release SCL.
while( !(PIN_USI & (1<<PIN_USI_SCL)) ); // Wait for SCL to go high.
_delay_us( T4_TWI/4 );
PORT_USI |= (1<<PIN_USI_SDA); // Release SDA.
_delay_us( T2_TWI/4 );

#ifdef SIGNAL_VERIFY
if( !(USISR & (1<<USIPF)) )
{
USI_TWI_state.errorState = USI_TWI_MISSING_STOP_CON;
return (FALSE);
}
#endif

return (TRUE);
}[/syntax]

Z góry dziękuje każdemu kto chce się podzielić wiedzą.

Statystyki: Napisane przez GoRo3 — 7 sie 2018, o 19:27

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